ASICs design for an MTD radar

Author

GuoRong, Hu ; LiTing, Han ; Yueqiu, Han ; Erke, Mao

Author_Institution

Dept. of Electron. Eng., Beijing Inst. of Technol., China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

69

Lastpage

72

Abstract

In an MTD (Moving Target Detect) radar, the digital signal processing is implemented by some real-time processing pipelines which consist of ASICs and FIFO or dual-port memory. We designed six ASICs with Xilinx FPGA, including the clutter-map unit former, the moving target signal extractor, the video signal integrator and the CFAR (Constant False Alarm Rate) operator. While all the timing and control are also realized by FPGA. With these ASICs, the system becomes small, efficient, easy to debug and now is working successfully in practical applications

Keywords

Doppler radar; application specific integrated circuits; field programmable gate arrays; integrated circuit design; pipeline processing; radar clutter; radar tracking; real-time systems; search radar; target tracking; ASIC design; CFAR operator; FIFO; MTD radar; Xilinx FPGA; clutter-map unit former; dual-port memory; moving target detect radar; moving target signal extractor; real-time processing pipelines; timing; video signal integrator; Application specific integrated circuits; Clutter; Digital signal processing; Field programmable gate arrays; Pipelines; Pulse compression methods; Radar detection; Radar signal processing; Signal design; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562753

Filename

562753