DocumentCode :
2946846
Title :
Bloom Filter Guided Transaction Scheduling
Author :
Blake, Geoffrey ; Dreslinski, Ronald G. ; Mudge, Trevor
Author_Institution :
Adv. Comput. Archit. Lab., Univ. of Michigan, Ann Arbor, MI, USA
fYear :
2011
fDate :
12-16 Feb. 2011
Firstpage :
75
Lastpage :
86
Abstract :
Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory system can experience live-lock, which is difficult to debug in parallel programs. Early work in contention management focused on heuristic managers that reacted to conflicts between transactions by picking the most appropriate transaction to abort. Reactive methods allow conflicts to happen repeatedly as they do not try to prevent future conflicts from happening. These shortcomings of reactive contention managers have led to proposals that approach contention management as a scheduling problem - proactive managers. Proactive techniques range from throttling execution in predicted periods of high contention to preventing groups of transactions running concurrently that are predicted likely to conflict. We propose a novel transaction scheduling scheme called “Bloom Filter Guided Transaction Scheduling” (BFGTS), that uses a combination of simple hardware and Bloom filter heuristics to guide scheduling decisions and provide enhanced performance in high contention situations. We compare to two state-of-the-art transaction schedulers, “Adaptive Transaction Scheduling” and “Proactive Transaction Scheduling” and show that BFGTS attains up to a 4.6× and 1.7× improvement on high contention benchmarks respectively. Across all benchmarks it shows a 35% and 25% average performance improvement respectively.
Keywords :
concurrency control; data structures; parallel programming; program debugging; scheduling; adaptive transaction scheduling; bloom filter guided transaction scheduling; contention management; parallel program debug; proactive transaction scheduling; reactive methods; throttling execution; transactional memory system; Benchmark testing; Data structures; Hardware; Memory management; Registers; Runtime; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on
Conference_Location :
San Antonio, TX
ISSN :
1530-0897
Print_ISBN :
978-1-4244-9432-3
Type :
conf
DOI :
10.1109/HPCA.2011.5749718
Filename :
5749718
Link To Document :
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