DocumentCode
2946985
Title
Symbolic analysis of faulty logic circuits in the presence of correlated gate failures
Author
Brkic, Srdan ; Ivanis, Predrag ; Djordjevic, Goran ; Vasic, Bane
Author_Institution
Innovation Centre, Univ. of Belgrade, Belgrade, Serbia
fYear
2013
fDate
26-28 Nov. 2013
Firstpage
369
Lastpage
372
Abstract
In this paper we present a method for symbolic analysis of unreliable logic circuits in the presence of correlated and data-dependent gate failures, described by Markov chains. Presented probabilistic algorithm is used for the analysis of majority logic and XOR logic circuits.
Keywords
Markov processes; circuit reliability; fault diagnosis; logic circuits; logic design; network analysis; probabilistic logic; Markov chains; XOR logic circuit; correlated gate failures; data-dependent gate failures; faulty logic circuit symbolic analysis; probabilistic algorithm; unreliable logic circuit; Circuit faults; Error probability; Logic circuits; Logic gates; Markov processes; Probabilistic logic; Combinatorial circuits; Markov chains; fault-tolerance; symbolic analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Telecommunications Forum (TELFOR), 2013 21st
Conference_Location
Belgrade
Print_ISBN
978-1-4799-1419-7
Type
conf
DOI
10.1109/TELFOR.2013.6716246
Filename
6716246
Link To Document