ASIC implementation of vector quantization for speaker recognition

This paper describes the high-level design and specification of an application-specific integrated circuit (ASIC) to implement a pattern matching algorithm based on vector quantization (VQ) and speaker verification algorithms. The ASIC uses a fully synchronous top-down design methodology with a hardware description language, ELLA. As well as presenting details of the algorithm and register-transfer level structure, the paper presents the hierarchical design methodology used to implement the algorithm in a low cost ASIC. The approach can be applied to a wide range of digital signal processing functions. The goal of is to develop a pattern matching system based on the VQ and codebooks which can be used as a alternative to the current software systems