DocumentCode :
2950958
Title :
Two-stage approach for 12 V VR
Author :
Ren, Yuancheng ; Xu, Ming ; Yao, Kaiwei ; Meng, Yu ; Lee, Fred C. ; Guo, Jinghong
Author_Institution :
Center for Power Electron. Syst., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Volume :
2
fYear :
2004
fDate :
2004
Firstpage :
1306
Abstract :
To meet the stringent specifications of the voltage regulator (VR), the two-stage approach is proposed for the 12 V VR. This paper discusses detailed design considerations, which include the design of the first stage, optimization of the intermediate bus voltage, design of the intermediate bus capacitors, and the design of the ultra-high frequency second stage. The analysis shows that the two-stage approach can realize high frequency, thus significantly reducing the output capacitance and therefore decreasing the cost. A 1.2 V/100 A prototype is built to verify the analysis. The second stage runs at 2 MHz per phase and the total efficiency is as high as 81%. Compared to the conventional single-stage multi phase buck, the two-stage approach is more cost effective and more efficient.
Keywords :
DC-DC power convertors; capacitors; network synthesis; voltage regulators; 1.2 V; 100 A; 12 V; 2 MHz; intermediate bus capacitors design; intermediate bus voltage optimization; output capacitance; single-stage multiphase buck; ultrahigh frequency second stage design; voltage regulator; Buck converters; Capacitors; Costs; Microprocessors; Power electronics; Regulators; Silver; Switching frequency; Virtual reality; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition, 2004. APEC '04. Nineteenth Annual IEEE
Print_ISBN :
0-7803-8269-2
Type :
conf
DOI :
10.1109/APEC.2004.1295992
Filename :
1295992
Link To Document :
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