Title :
A column-parallel SA ADC with linearity calibration for CMOS imagers
Author :
Shan-Ju Tsai ; Yen-Chun Chen ; Chih-Cheng Hsieh ; Wen-Hsu Chang ; Hann-Huei Tsai ; Chin-Fong Chiu
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
This paper presents a 10-bit column-parallel successive approximation analog-to-digital converter (SA-ADC) with linearity calibration for CMOS imager. A multiple segmented charge redistribution capacitive digital-to-analog converter (MS-C-DAC) is utilized to reduce the DAC array size. A new linearity calibration method with adaptive reset configuration (ARC) of DAC is also proposed to solve the inherent mismatch issue of segmented DAC. The calibration technique ARC effectively eliminates three types of DAC error, i.e. (1) inaccurate serial capacitances, (2) parasitic capacitance on the charge conservation nodes, (3) mismatch of MSB capacitance. A prototype chip has been fabricated and verified in 0.18um CMOS technology. The new calibration method improves DNL from +5.62/-0.48 LSB to +0.33/-0.4 LSB, INL from +3.44/-4.93 LSB to +0.07/-1.81 LSB and SNDR from 46.63dB to 51.27dB at 240kS/s sampling rate. The whole chip consumes 35.46uW at a single 1.8V supply operation.
Keywords :
CMOS image sensors; analogue-digital conversion; calibration; digital-analogue conversion; CMOS imager; MSB capacitance mismatch; adaptive reset configuration; charge conservation node; column parallel SA ADC; inaccurate serial capacitance error; linearity calibration; multiple segmented charge redistribution capacitive digital-analog converter; parasitic capacitance; power 35.46 muW; size 0.18 mum; successive approximation analog-digital converter; voltage 1.8 V; Arrays; CMOS integrated circuits; Calibration; Capacitors; Linearity; Parasitic capacitance;
Conference_Titel :
Sensors, 2012 IEEE
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1766-6
Electronic_ISBN :
1930-0395
DOI :
10.1109/ICSENS.2012.6411448