H.264/AVC Eighth Pixel MC Chrominance interpolation hardware targeting very high resolution videos

Author

Schoenknecht, Mateus Thurow ; Timm, éric Falchi ; Rosa, Leomar Soares da, Jr. ; Agostini, Luciano Volcan

Author_Institution

Group of Archit. & Integrated Circuits - GACI, Fed. Univ. of Pelotas - UFPel, Pelotas, Brazil

fYear

2011

fDate

23-25 Feb. 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a hardware design for the H.264/AVC Eighth-Pixel Chrominance Interpolation Unit that is a part of the Motion Compensation Unit. The architecture was optimized to reach a high throughput through a balanced pipeline and internal parallelism exploration. The design was described in VHDL and synthesized to a Xilinx Virtex2p FPGA. The best performance results achieve an operation frequency of 100 MHz, processing up to 42 QHDTV frames (3840×2048 pixels) per second.

Keywords

field programmable gate arrays; hardware description languages; high definition television; image resolution; motion compensation; pipeline processing; video coding; H.264/AVC eighth pixel MC chrominance interpolation hardware; QHDTV frames; VHDL; Xilinx Virtex2p FPGA; balanced pipeline; internal parallelism exploration; motion compensation unit; very high resolution videos; Automatic voltage control; Computer architecture; Hardware; Interpolation; Motion estimation; Pixel; Videos; H.264/AVC; eighth-pixel interpolation; hardware design; motion compensation; video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2011 IEEE Second Latin American Symposium on

Conference_Location

Bogata

Print_ISBN

978-1-4244-9484-2

Type

conf

DOI

10.1109/LASCAS.2011.5750288

Filename

5750288