Switching activity propagation of VHDL-RTL combinational designs through an automated tool

A probabilistic method and a tool for switching activity propagation of VHDL-RTL combinational designs is presented. The propagation of switching activities is performed through the extraction of the BDD (binary decision diagram) of the circuit logic. In order to avoid the memory explosion of BDDs, a novel representation for the switching activity which results in smaller BDDs is proposed. In addition, an automatic circuit partition of the circuit is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. The tool is integrated in a design environment to support methods to improve the quality of VHDL based designs and reduce design time. The presented tool will be the base for further power and testability analysis, and estimation tools.