• DocumentCode
    2952665
  • Title

    An ultra low energy 9T half-select-free subthreshold SRAM bitcell

  • Author

    Banerjee, Adrish ; Calhoun, Benton H.

  • Author_Institution
    Univ. of Virginia, Charlottesville, VA, USA
  • fYear
    2013
  • fDate
    7-10 Oct. 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Operating both logic and memory at subthreshold supply voltages reduces energy dissipation for portable medical devices where battery life is critical. In this paper, we propose a 9T half-select-free subthreshold bitcell that has 2.05X lower mean read energy, 12.39% lower mean write energy, and 28% lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.
  • Keywords
    SRAM chips; leakage currents; low-power electronics; radiation hardening (electronics); bitline interleaving technique; half-select-free subthreshold SRAM bitcell; leakage current; soft errors; ultralow mean energy; Arrays; Batteries; Government; Leakage currents; Measurement; Random access memory; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
  • Conference_Location
    Monterey, CA
  • Type

    conf

  • DOI
    10.1109/S3S.2013.6716577
  • Filename
    6716577