A compact modeling of drain current in PD/FD SOI MOSFETs

In this paper, a unified analytical I-V model for silicon-on-insulator (SOI) MOSFET is presented. The model is valid for possible transitions between partially-depleted (PD) and fully-depleted (FD) modes during the transistor operation. It is based on a non-pinned surface potential approach that is valid for all regions of operation. The surface potential is calculated accurately and efficiently in this model where small geometry effects such as channel length modulation (CLM) and high field mobility effects are also included. It also considers the self-heating effect, which is important for complete modeling of SOI devices. For including the floating body effect, the parasitic currents in each mode of operation is modeled with a proper formulation while a smoothing function is invoked for the transition between the operation modes. A comparison between the model and the experimental results shows good agreement over a wide range of drain and gate voltages.