Using the C language to reduce the design cycle of an MPEG-2 video IC: a case study

Designing a very large chip requires very long simulation time. For example, to simulate an MPEG-2 video decompression circuit using the Verilog simulator on a top-of-the-line workstation (using Ross 150 MHz CPU with 256 MB memory) takes 24 hours to produce one frame (704×480) of data. One minute worth of video will need 5 years of Verilog time. Facing this impossibility, we adopted a methodology in which a hardware model of MPEG described in the C language is developed in parallel with the HDL design. Cross verification of the C and the HDL descriptions led to increased confidence. Eventually, simulation was driven by the C description: the C model was used to screen MPEG-2 bitstreams and to identify new test cases for Verilog simulation. The reduction of simulation time makes the design cycle manageable