DocumentCode :
2957188
Title :
Combinational ATPG acceleration by dynamic circuit partition
Author :
Xiaolin, Wang ; Huihua, Yu ; Chengfang, Yu
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
fYear :
1996
fDate :
21-24 Oct 1996
Firstpage :
413
Lastpage :
416
Abstract :
If no FOS exists in the circuit under test, the execution time of DTM and STM linearly increase proportional to circuit size. The non-linear factors in the algorithm are introduced by FOSs. To limit the affection of FOS´s as small as possible, a technique called Dynamic Search Space Reduction is introduced in this paper and only the FOSs who have more then two branches in the sensitive region have to be considered. The number of these FOSs usually very small because some of FOSs have been isolated by the search space reduction algorithm. In the meantime, we notice that the faults behind an FOS with two or more branches in the sensitive region are always testable if the fault can be propagate to the FOS without modify the associate line values along the sensitive paths
Keywords :
automatic testing; combinational circuits; integrated circuit testing; logic partitioning; logic testing; DTM; FOS; STM; circuit under test; combinational ATPG acceleration; dynamic circuit partition; dynamic search space reduction algorithm; fault testing; nonlinear factor; Acceleration; Automatic test pattern generation; Circuit analysis; Circuit faults; Circuit testing; Controllability; Nonlinear dynamical systems; Observability; Partitioning algorithms; Statistical analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
Type :
conf
DOI :
10.1109/ICASIC.1996.562840
Filename :
562840
Link To Document :
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