Title :
A low-power SRAM using improved charge transfer sense amplifiers and a dual-Vth CMOS circuit scheme
Author :
Fukushi, I. ; Sasagawa, R. ; Hamaminato, M. ; Izawa, T. ; Kawashima, S.
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
In this paper we propose an improved version of the charge transfer sense amplifier (CT sense amp) which completely compensates the threshold voltage (Vth) difference of MOSFETs. We also present a dual-Vth CMOS circuit scheme that enables high speed operation and low leakage power consumption at low supply voltage. A low-power, low-voltage 2 k/spl times/16 b SRAM macro was designed and fabricated using a 0.25 /spl mu/m process. It showed stable operation with an access time of 7.0 ns and power consumption of 3.9 mW at 1.0 V (boost 1.5 V), 100 MHz, 85/spl deg/C.
Keywords :
CMOS memory circuits; SRAM chips; high-speed integrated circuits; 0.25 micron; 1 to 1.5 V; 100 MHz; 3.9 mW; 32 kbit; 7 ns; 85 C; charge transfer sense amplifiers; dual-Vth CMOS circuit scheme; high speed operation; low leakage power consumption; low-power SRAM; stable operation; threshold voltage compensation; Charge transfer; Circuits; Differential amplifiers; Energy consumption; FETs; Latches; MOS devices; Pulse amplifiers; Random access memory; Threshold voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688039
