Title :
A 480 MHz 11 mW PR4 Viterbi detector and margin circuit in 0.25 /spl mu/m CMOS
Author_Institution :
IBM Almaden Res. Center, San Jose, CA, USA
Abstract :
This paper describes a Viterbi detector and margin circuit for PR4 magnetic recording channels. The implementation uses a modified difference-metric formulation of the Viterbi algorithm (VA). A Viterbi margin (VM) function is included for channel quality checking purposes. Modifications and implementation techniques that optimize power consumption and speed are described. The VA+VM circuit includes 24+24 bits of path and margin memory, uses 11 mW of power (7 mW for VA alone) at 480 MHz and occupies 0.052 mm/sup 2/ in a 0.25 /spl mu/m 1.8 V CMOS process.
Keywords :
CMOS digital integrated circuits; Viterbi detection; magnetic recording; partial response channels; 0.25 mum; 1.8 V; 11 mW; 480 MHz; CMOS process; PR4 Viterbi detector; channel quality checking; magnetic recording channels; margin circuit; modified difference-metric formulation; partial response recording; power consumption; CMOS process; Circuits; Clocks; Code standards; Costs; Detectors; Magnetic heads; Maximum likelihood detection; Virtual manufacturing; Viterbi algorithm;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688040
