Realization of bidirectional associative memory using a pseudo-parallel searching approach

A simple and high speed realization of bidirectional associative memory (BAM) with dynamic storage is presented. Although the BAM has been proved to be a stable system, the capacity of the BAM is small if the original evolutions are employed. Hence, in order not to lose any of the capacity of the BAM, the authors consider the simplicity of the design, the speed of the architecture, and the pseudo-parallel searching in this implementation. Only digital circuits are employed in this chip. MAGIC layouts of the chip and IRSIM simulation results are presented, which confirms the performance of the chip design. The proposed architecture for the implementation turns out to be a scalable, regular, and dense design