Submicron wiring technology with tungsten and planarization

Author

Kaanta, Carter ; Cote, William ; Cronin, John ; Holland, Karey ; Lee, Pei-Ing ; Wright, Terry

Author_Institution

IBM, Essex Junction, VT, USA

fYear

1988

fDate

13-14 June 1988

Firstpage

21

Lastpage

28

Abstract

A versatile wiring technology has been developed which is suitable for high-density memory and multilevel logic applications. This fully integrated technology features CVD-tungsten (W) and planarization. Virtual W studs maximise density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability. The chosen materials and process combinations make possible aggressive metal pitch for DRAM, reliable space saving vertical studs for contact/via intensive SRAM, and provide vertical wiring for high-density multilevel logic. Device and reliability results are presented.<>

Keywords

VLSI; circuit reliability; integrated circuit technology; metallisation; tungsten; CVD; DRAM; SRAM; W; circuit performance; contact/via ground rules; high-density memory; multilevel logic; patterning; planarization; reliability; submicron wiring technology; thick insulators; vertical studs; vertical wiring; Capacitance; Circuit optimization; Insulation; Integrated circuit technology; Integrated circuit yield; Logic; Planarization; Random access memory; Tungsten; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14172

Filename

14172