A 2-6 GHz CMOS factorial delay locked loop dedicated to multi-standard frequency synthesis

A 2-6 GHz multi-standard CMOS frequency synthesizer using a programmable factorial delay locked loop (DLL) is presented. The performances of the architecture have been successfully demonstrated according to behavioral model. This architecture has a 100 MHz, square wave clock reference and provides two outputs both in phase and in quadrature by multiplying the reference by a programmable factor. For an output frequency range from 2 up to 6 GHz, simulations confirm the acquisition process of the overall structure, the good frequency stability and the DLL mode functionality.