Strategy to disentangle multiple faults to identify random defects within test structures

Defect inspection is required for process control and to enhance chip yield. Electrical measurements at test structures are commonly used to detect faults. To improve the accuracy in order to evaluate the defects that have caused such faults, this paper presents a strategy to analyze single and multiple faults to precisely determine the number, layer and location of randomly distributed defects within a test structure layout. For this purpose, we first discuss the possibilities for fault analysis within known test structure layouts. We then present modified test structure layouts to improve the analysis of multiple faults. Finally, we introduce a methodology to disentangle multiple faults by calculating and comparing the probability of possible defect locations within large test structure layout areas