Electrical design methodology of a 407 pin multi-layer ceramic package

A multilayer ceramic package capable of providing up to 350 I/O connections at a frequency of up to 60 MHz is discussed. The package supports driver risetimes of 1 ns and is compatible with conventional through-hole assembly processes. The critical parameters are propagation delay, ground path inductance, power supply inductance to bypass capacitor, near-end and far-end crosstalk, and the degree of isolation between power supplies. The final design of the package consisted of 12 metallization layers distributed among power, ground and signal-routing planes. Readily available software was used for the design. The design, layout, modeling, and simulation analysis was done on HP 9000 series 300 computers