DocumentCode
2959770
Title
A sequential solution methodology for capacity allocation and lot scheduling problems for photolithography
Author
Akçali, Elif ; Uzsoy, Reha
Author_Institution
Sch. of Ind. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2000
fDate
2000
Firstpage
374
Lastpage
381
Abstract
In this paper, we study the shift scheduling problem for photolithography workcenters, which involves specifying the start and finish times for individual lots over the duration of the shift. For the schedule to be accurate, the operational policies (such as set-up control policies) and auxiliary resources of the workcenter (such as reticles) must be considered, which further complicates the problem. We present a sequential procedure that separates the problem into capacity allocation and lot sequencing sub-problems. Although solving these problems sequentially is not a new idea, the lack of empirical evidence of the benefits and insight into implementation issues motivate this research. We use a simulation model of a wafer fabrication facility to examine the effects of using this procedure for scheduling of the photolithography operations. We show that the procedure is a viable method to schedule photolithography workcenter. The choice of the time horizon over which the capacity allocation problem is solved affects cycle time metrics and the number of set-ups significantly. However, varying reticle and set-up constraints has little impact. Finally, we show that the procedure is sensitive to the structure of the operation-stepper matrix and suggest a remedy to overcome the problem
Keywords
integrated circuit manufacture; manufacturing resources planning; photolithography; production control; reticles; semiconductor process modelling; auxiliary resources; capacity allocation; cycle time metrics; lot finish time; lot scheduling; lot start time; operation-stepper matrix; operational policies; photolithography; photolithography operation; photolithography workcenters; reticle constraints; reticles; sequential procedure; sequential solution methodology; set-up constraints; set-up control policies; shift scheduling; simulation model; wafer fabrication facility; Availability; Biographies; Furnaces; Industrial engineering; Job shop scheduling; Lithography; Manufacturing industries; Optimization methods; Production planning; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International
Conference_Location
Santa Clara, CA
ISSN
1089-8190
Print_ISBN
0-7803-6482-1
Type
conf
DOI
10.1109/IEMT.2000.910749
Filename
910749
Link To Document