Title :
Performance evaluation of the communications protocol processor
Author :
Mandalia, Baiju D. ; Ilyas, Mohammad ; Fernandez, Eduardo B. ; Khoshgoftaar, Taghi
Author_Institution :
IBM Corp., Boca Raton, FL, USA
Abstract :
The performance evaluation of the protocol processing elements of a multimedia communications processor, is described. Specialized frame and header processing units were simulated using a high-level hardware model to produce typical path lengths for known protocols. A performance evaluation based on extrapolated data was performed to evaluate variable traffic and application conditions. The results indicate that such an architecture can allow handling of data for 5-10-Mb/s links without modification of existing protocols. The variation would depend on the number of layers supported
Keywords :
microprocessor chips; performance evaluation; protocols; telecommunications computing; 5 to 10 Mbit/s; communications protocol processor; frame processing units; header processing units; high-level hardware model; multimedia communications processor; path lengths; performance evaluation; Computer architecture; Cyclic redundancy check; Data communication; Hardware; Multimedia communication; Optical computing; Protocols; Registers; Telecommunication traffic; Traffic control;
Conference_Titel :
Global Telecommunications Conference, 1990, and Exhibition. 'Communications: Connecting the Future', GLOBECOM '90., IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
0-87942-632-2
DOI :
10.1109/GLOCOM.1990.116634
