DocumentCode
2961009
Title
Bus architecture for 600-MHz 4.5-Mb DDR SRAM
Author
Kawasumi, A. ; Suzuki, A. ; Hatada, H. ; Kobayashi, T. ; Takeyama, Y. ; Hirabayashi, O. ; Hamano, T. ; Otsuka, N.
Author_Institution
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
fYear
1998
fDate
11-13 June 1998
Firstpage
178
Lastpage
179
Abstract
A double data rate (DDR) SRAM bus architecture which can eliminate any speed penalty for doubling the I/O frequency and support single data rate (SDR) compatibility has been proposed. A method to guarantee data coherency for both DDR and SDR has also been described. With this architecture, we developed a 4.5 Mb DDR SRAM. Under the typical 2.5 V condition, a 600 MHz I/O frequency was achieved.
Keywords
SRAM chips; VLSI; high-speed integrated circuits; memory architecture; 2.5 V; 4.5 Mbit; 600 MHz; DDR SRAM; SRAM bus architecture; data coherency; double data rate memory; single data rate compatibility; static RAM; Circuits; Clocks; Data communication; Data engineering; Delay; Frequency; Laboratories; Microelectronics; Random access memory; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4766-8
Type
conf
DOI
10.1109/VLSIC.1998.688075
Filename
688075
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