Title :
A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock
Author :
Nakamura, K. ; Fukaishi, M. ; Abiko, H. ; Matsumoto, A. ; Yotsuyanagi, M.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
We developed a new phase detector which can perform 1:2 data demultiplexing function. A newly developed pulse compensation technique enables one to output the analog phase difference for a half-frequency clock. This circuit can be used as both a phase detector for a PLL clock recovery circuit (CRC) and a root module for an asynchronous tree-type DEMUX. Using a new combined CRC-DEMUX structure, we achieved 6 Gbps 1:8 DEMUX with CRC using a 0.18 /spl mu/m CMOS in 83 mW power consumption.
Keywords :
CMOS integrated circuits; asynchronous circuits; demultiplexing equipment; large scale integration; mixed analogue-digital integrated circuits; phase detectors; phase locked loops; 0.18 micron; 6 Gbit/s; 83 mW; CMOS; CRC-DEMUX structure; PLL clock recovery circuit; analog phase difference; data demultiplexing function; half-frequency clock; phase detecting DEMUX module; power consumption; pulse compensation technique; root module; Clocks; Cyclic redundancy check; Demultiplexing; Detectors; Information retrieval; Phase detection; Phase locked loops; Pulse circuits; Space vector pulse width modulation; Timing;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688081
