Title :
A jitter and data duty distortion tolerated PLL circuit for 156-Mbps burst-mode transmission
Author :
Sato, M. ; Aoki, Yuya ; Baba, M. ; Wakayama, Y. ; Saikusa, N. ; Kayano, M. ; Murakami, S.
Author_Institution :
NEC Telecom Syst. Ltd., Kanagawa, Japan
Abstract :
A new PLL circuit for 156-Mbps burst-mode transmission application in a passive optical network (PON) is described in this paper. For data recognition accuracy and jitter tolerance, we propose an ADR (adaptive data recognition) circuit using rising and falling phase average values extracted from input burst-mode data, and an EPA (edge phase averaging) circuit averaging rising and falling edge phases of input burst-mode data. The PLL circuit has been implemented on 3.3 V, 0.35 /spl mu/m CMOS standard cell, and has shown good system performance, such as a power penalty of less than 0.1 dB at 10/sup -8/ error rate.
Keywords :
CMOS digital integrated circuits; digital communication; digital phase locked loops; digital subscriber lines; electric distortion; optical communication equipment; optical fibre subscriber loops; timing jitter; 0.35 micron; 156 Mbit/s; 3.3 V; CMOS standard cell technology; PLL circuit; PON; adaptive data recognition circuit; burst-mode transmission; data duty distortion tolerant circuit; data recognition accuracy; edge phase averaging circuit; jitter tolerance; jitter tolerant circuit; optical access network; passive optical network; Circuits; Clocks; Detectors; Jitter; National electric code; Passive optical networks; Phase detection; Phase locked loops; Sampling methods; Signal generators;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688087
