Novel high-radix residue number system multipliers and adders

Radix-r modulo rⁿ multipliers and adders are introduced in this paper. The proposed architectures are shown to require several times less area than previously reported architectures, for particular moduli of operation. The proposed architectures are preferable in an area-time sense for several cases. The complexity reduction is achieved by extending the carry-ignore property of modulo 2ⁿ operations to radices higher than 2, but not powers of 2. Detailed hardware complexity models are offered