Impact of context dependenent variability in CMOS embedded with SiGe on circuit performance & power

For CMOS circuits, the increase in power consumption has been curtailed in recent years by introducing mechanical stress to achieve device speed gain over and above the traditional speed vs. power tradeoffs achieved only by scaling gate lengths. Starting with the 90 nm silicon node, induced compressive stress by embedded SiGe is being used to increase the hole mobility in PMOS. Because of the context dependence of this stress, local variability of the device parameters is expected to increase with this process method. In this paper, we discuss a method of direct measurement of the channel stress using Synchrotron X-ray diffraction and show the impact of resulting increased mobility and increased local variation on the circuit performance using Monte Carlo SPICE simulations of CMOS invertor based as well as NAND based ring oscillators. Simulation results demonstrate how lower supply voltage can be used to meet performance targets with lower power consumption.