Pre-conditioning Free Footless DCVSL for High-performance Datapaths

We present a footless DCVSL logic with preconditioning free self-timed scheme. The proposed footless DCVSL employs self-timed precharge control logic to precharge DCVSL nMOS pull-down network. The footless DCVSL is free from timing generator to generate precharge signal after all the input signals become 0, which is required for the conventional footless DCVSL logics. The proposed footless DCVSL achieves 4.5% delay improvement for FO8 logic chain using 90 nm CMOS process without any complex delay tuning circuits.