Frequency Response Analysis of Latch Utilized in High-Speed Comparator

Author

Okura, Shunsuke ; Ohkura, Tetsuro ; Taniguchi, Kenji ; Shibata, Hajime

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

1077

Lastpage

1080

Abstract

We investigated the dynamic nature of a highspeed CMOS comparator, and present a comparator frequency-response model based on small-signal linear analysis of a latch. The analytical frequency model offers good insight into the linearity of the quantizer utilized in CTDeltaSigma modulators. In addition, a novel design guideline for a high-speed CMOS comparator to ensure the quantizer linearity is presented.

Keywords

CMOS analogue integrated circuits; comparators (circuits); delta-sigma modulation; flip-flops; frequency response; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; quantisation (signal); CTDeltaSigma modulators; analytical frequency model; closed-loop continuous-time delta sigma modulators; dynamic nature analysis; frequency response analysis; high-speed CMOS comparator design; latch; quantizer; small-signal linear analysis; Analytical models; Circuits; Frequency response; Guidelines; Latches; Linearity; Metastasis; Semiconductor device modeling; Signal analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0395-2

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379625

Filename

4263557