A Wide-Range Delay-Locked Loop with a New Lock-Detect Circuit

This paper describes a wide frequency range and low jitter delay-locked loop. A new architecture is proposed for lock-detect circuit that solves the problem of false locking associated with conventional DLLs. The exact 50% duty cycle is not necessary for the correct operation of this architecture. The circuit design and ADS simulation are based upon TSMC 0.18mum CMOS process. The simulation results show that the proposed DLL has a wide locking range 120 to 420 MHz. Moreover rms jitter is as low as 1.2 ps at 420 MHz.