High-performance PQFP

Author

Mallik, Debendra ; Bhattacharyya, Bidyut K.

Author_Institution

Intel Corp., Chandler, AZ, USA

fYear

1989

fDate

22-24 May 1989

Firstpage

494

Lastpage

503

Abstract

The design of a high-performance plastic quad flat back (PQFP) is described. It is a multilayer package designed to provide a high level of electrical and thermal performance. The design maintains the JEDEC standard package outline; the changes are internal to the plastic body of the PQFP. A pair of parallel metal planes is added to serve as the power and ground paths for the device. By replacing a substantial portion of the highly inductive leads by the plane and shorting all V_cc or V_ss leads through their respective planes the power-group loop inductance is reduced significantly. The planes increase the power-ground capacitance by approximately 500% while lowering the capacitive coupling between leads. The planes spread the heat generated by the IC chip over the total area of the package, reducing the package thermal resistance and eliminating the need for internal heats conductors

Keywords

VLSI; integrated circuit technology; packaging; standards; IC chip; JEDEC standard package outline; PQFP; electrical performance; high pin count VLSI device; multilayer package; package thermal resistance; plastic quad flat back; power-ground capacitance; power-group loop inductance; thermal performance; Assembly; Bonding; Electronics packaging; Gold; Integrated circuit packaging; Manufacturing; Plastic packaging; Thermal resistance; Variable structure systems; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components Conference, 1989. Proceedings., 39th

Conference_Location

Houston, TX

Type

conf

DOI

10.1109/ECC.1989.77796

Filename

77796