Sample and Hold design techniques for Nyquist ADC design

With the continuous reduction in analog supply level of recent CMOS processes, the Sample and Hold (S/H) circuit used in high performance ADC suffers from smaller swing and lower dynamic range. In most high speed (Nyquist) ADCs, the S/H stage is the most crucial circuit affecting distortion and noise. This paper describes 2 techniques which improve the performance of the input sampling switch. The performance of these techniques has been verified and demonstrated through circuit simulations in 0.13 um CMOS process.