Title :
A mixed mode design flow for multi GHz ADPLLs
Author :
Shakir, Muhammad ; Abdulaziz, Mohammed ; Lu, Ping ; Andreani, Pietro
Author_Institution :
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
Abstract :
A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.
Keywords :
CMOS integrated circuits; UHF integrated circuits; clocks; digital phase locked loops; integrated circuit design; mixed analogue-digital integrated circuits; CMOS process technology; DCO; TDC; all digital phase locked loop; current 2.5 mA; digital cell; digitally controlled oscillator; divider-by-two output clock; frequency 2.7 GHz; mixed mode digital design flow; multiGHz ADPLL; size 90 nm; systematic design approach; time to digital converter; voltage 1.2 V;
Conference_Titel :
NORCHIP, 2011
Conference_Location :
Lund
Print_ISBN :
978-1-4577-0514-4
Electronic_ISBN :
978-1-4577-0515-1
DOI :
10.1109/NORCHP.2011.6126714
