Yield modeling and yield-aware mapping for application specific networks-on-chip

Network-on-chip has been proposed as an interconnection solution for increasing number of cores on chips. Increasing number of cores affects the yield of the devices and systems that make use of the multi core chips. Two major factors that affect the system yield are routers and links yield. We propose a yield model which uses variable router yield for the system. Based on this model, a yield aware mapping is proposed. Our proposed mapping algorithm improves yield up to 30 percent. Although the algorithm has decreased power consumption up to 15 percent, it has caused delay to increase 39 percent.