A GALS ASIC implementation from a CAL dataflow description

This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation.