DocumentCode :
2963036
Title :
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
Author :
Abdulaziz, Mohammed ; Shakir, Muhammad ; Lu, Ping ; Andreani, Pietro
Author_Institution :
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
fYear :
2011
fDate :
14-15 Nov. 2011
Firstpage :
1
Lastpage :
4
Abstract :
A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.
Keywords :
delta-sigma modulation; phase locked loops; CMOS process technology; delta sigma modulator; digitally controlled oscillator; divider-less all digital phase-locked loop; frequency 2.7 GHz; frequency 20 kHz; frequency 625 GHz; high frequency resolution; power 7.6 mW; size 90 nm; source-varactor LC resonant tank; standard digital design; time to digital converter; voltage 1.2 V; Clocks; Frequency conversion; Frequency estimation; Manuals; Switches; Time frequency analysis; Tuning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP, 2011
Conference_Location :
Lund
Print_ISBN :
978-1-4577-0514-4
Electronic_ISBN :
978-1-4577-0515-1
Type :
conf
DOI :
10.1109/NORCHP.2011.6126743
Filename :
6126743
Link To Document :
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