• DocumentCode
    2963255
  • Title

    Simulation based multiobjective schedule optimization in semiconductor manufacturing

  • Author

    Gupta, Amit K. ; Sivakumar, Appa Iyer

  • Author_Institution
    Sch. of Mech. & Production Eng., Nanyang Technol. Univ., Singapore
  • Volume
    2
  • fYear
    2002
  • fDate
    8-11 Dec. 2002
  • Firstpage
    1862
  • Abstract
    In semiconductor manufacturing, it requires more than one objective such as cycle time, machine utilization and due date accuracy to be kept in focus simultaneously, while developing an effective scheduling. In this paper, a near optimal solution, which is not inferior to any other feasible solutions in terms of all objectives, is generated with a combination of the analytically optimal and simulation based scheduling approach. First, the job shop scheduling problem is modeled using the discrete event simulation approach and the problem is divided in to simulation clock based lot selection sub-problems. Then, at each decision instant in simulated time, a Pareto optimal lot is selected using the various techniques to deal with multiobjective optimization such as weighted aggregation approach, global criterion method, minimum deviation method, and compromise programming. An illustration shows how these techniques work effectively in solving the multiobjective scheduling problem using discrete event simulation.
  • Keywords
    discrete event simulation; manufacturing data processing; optimisation; production control; scheduling; semiconductor device manufacture; Pareto optimal lot; compromise programming; cycle time; discrete event simulation; due date accuracy; global criterion method; job shop scheduling; lot selection; machine utilization; minimum deviation method; multiobjective optimization; semiconductor manufacturing; simulation based multiobjective schedule optimization; weighted aggregation approach; Analytical models; Assembly; Computational modeling; Discrete event simulation; Integrated circuit testing; Job shop scheduling; Optimal scheduling; Pareto optimization; Semiconductor device manufacture; Virtual manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation Conference, 2002. Proceedings of the Winter
  • Print_ISBN
    0-7803-7614-5
  • Type

    conf

  • DOI
    10.1109/WSC.2002.1166480
  • Filename
    1166480