Considerations on package design for high speed and high pin count CMOS devices

Author

Sudo, Toshio ; Mori, Toshiaki ; Yoshimori, Takashi

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1989

fDate

22-24 May 1989

Firstpage

531

Lastpage

538

Abstract

High-speed, high-density CMOS VLSI devices have powerful output buffers to charge a load capacitance quickly, which causes large switching noise on the power/ground lines. Furthermore, the equivalent impedance of the output buffer becomes lower than the characteristic impedance of the transmission line on a board, which induces complicated phenomena, including ringing noise. These problems are discussed, and the electrical characteristics of a 348-pin QFP (quad flat package) developed for a 1-micron, 129-K gate CMOS gate array is described. The factors that determine switching noise were investigated by simulation that represents the packaging noise was designed and used to characterize the 348-pin QFP. Disagreement between measured data and simulation results remains to be investigated

Keywords

CMOS integrated circuits; VLSI; electron device noise; integrated circuit technology; logic arrays; packaging; CMOS gate array; QFP; characteristic impedance; electrical characteristics; high pin count CMOS devices; high speed CMOS device; high-density CMOS VLSI devices; package design; quad flat package; ringing noise; simulation; switching noise; transmission line; CMOS logic circuits; Capacitance; Circuit noise; Crosstalk; Electronics packaging; Logic devices; Semiconductor device modeling; Switches; Very large scale integration; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components Conference, 1989. Proceedings., 39th

Conference_Location

Houston, TX

Type

conf

DOI

10.1109/ECC.1989.77801

Filename

77801