DocumentCode
29636
Title
Erratum to “Test Time Reduction in EDT Bandwidth Management for SoC Designs” [Nov 13 1776-1786]
Author
Janicki, Jakub ; Kassab, M. ; Mrugalski, Grzegorz ; Mukherjee, Nandini ; Rajski, J. ; Tyszer, J.
Author_Institution
Faculty of Electronics and Telecommunications, Poznań University of Technology, Poznań, Poland
Volume
33
Issue
1
fYear
2014
fDate
Jan. 2014
Firstpage
167
Lastpage
167
Abstract
Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.
Keywords
Automatic test equipment; Bandwidth; Integrated circuit testing; Optimization; System-on-chip;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2013.2292631
Filename
6685876
Link To Document