Direct digital frequency synthesizer architecture based on Chebyshev approximation

This paper presents a Chebyshev approximation based method for digital quadrature sine and cosine waveform synthesis. The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with register transfer level VHDL. Simulation and synthesis results of the Chebyshev sinusoidal signal synthesizer are presented and compared with other direct digital sine and cosine synthesizers. The synthesis is carried out on a 0.35 /spl mu/m, 3.3 V, 4-metal, n-well standard cell process. According to the synthesis results the total design area is 5900 gates and the maximum system clock frequency 160 MHz.