Study on Effect of Via Contour Distortion on Via Micro-void Formation in 45nm-node Process

Author

Kunishima, H. ; Tagami, M. ; Shin, T. ; Goto, Y. ; Oshima, K. ; Nishimura, T. ; Miyamori, Y. ; Enomoto, Y. ; Ema, T. ; Yamada, N. ; Akiyama, K. ; Okada, N.

Author_Institution

NEC Electron. Corp., Sagamihara

fYear

2007

fDate

4-6 June 2007

Firstpage

161

Lastpage

163

Abstract

We have investigated micro-void formation mechanism in vias at 45 nm-node using OBIRCH method and SEM analysis, and found that micro-void formation is induced by via contour distortion. We have also clarified the correlation between edge roughness of a via pattern and micro-void formation. From this, we conclude that via edge roughness suppression is the key technology for robust interconnects fabrication in 45 nm-node and beyond.

Keywords

integrated circuit interconnections; integrated circuit reliability; scanning electron microscopy; voids (solid); OBIRCH method; SEM analysis; contour distortion; edge roughness; integration technologies; interconnects fabrication; microvoid formation; optical beam induced resistance change method; Companies; Degradation; Electric resistance; Electrical resistance measurement; Fabrication; National electric code; Pattern analysis; Robustness; Testing; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382378

Filename

4263690