VLSI design optimization of input/output-buffered broadband ATM switches

We explore what is needed to improve and automate the process of designing a broadband ATM switch, i.e., determining the “optimal” switch parameters given hardware costs and constraints on quality of service. We present a cost model for implementation with CMOS integrated circuits, based on some prototype designs that include both input and output buffering, and combine this with a simple method for rough performance analysis to allow quick design evaluation. Experiments are presented for a range of specifications, based on an automated exhaustive search algorithm and a framework for using nonlinear integer optimization to improve efficiency in the future is developed