New memory sense amplifier designs in CMOS technology

Author

Tsiatouhas, Y. ; Chrisanthopoulos, A. ; Kamoulakos, G. ; Haniotakis, Th

Author_Institution

Adv. Silicon Solutions Div., Integrated Syst. Dev. SA, Athens, Greece

Volume

1

fYear

2000

fDate

2000

Firstpage

19

Abstract

In this paper two-stage sense amplifier designs are proposed which are suitable for current sensing in SRAM and flash memories read operations. The first-stage of these sense amplifiers is characterized by its low power operation and its small area overhead which requires only three transistors in the pitch of a bit line pair for the sensing of the stored data in the selected memory cell. Compact layout designs and simulations in 0.25 μm CMOS technology have been carried out to evaluate the efficiency of the proposed schemes

Keywords

CMOS memory circuits; SRAM chips; current mirrors; flash memories; integrated circuit design; low-power electronics; 0.25 micron; CMOS technology; SRAM; area overhead; bit line pair; current sensing; efficiency; flash memories; layout designs; low power operation; memory sense amplifier designs; read operations; two-stage sense amplifier; CMOS technology; Capacitance; Circuit simulation; Delay; Flash memory; Low voltage; Operational amplifiers; Signal design; Synthetic aperture sonar; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911469

Filename

911469