Performance analysis for a packet mode combined input-output queued switch

In this paper we propose and analyze a CIOQ switch for the scheduling of both cells and variable-length packets. This architecture is based on a cell-based ATM core, and the variable-length packet is represented as a sequence of AAL5 cells. During the packet switching, individual cells destined to other cell-based ports will not be affected and thus all the benefits in traditional VOQ switches still apply. We analyze the delay, forwarding, and throughput through the classical queueing model. According to our analysis, the average delay and throughput of packet scheduling depends on the channel utilization and expected packet length only. Since the performance is independent of the switch size, it is ideal for handling large number of switching ports.