DocumentCode :
2966869
Title :
A unified systolic array design for wavelet-based video codec
Author :
Tai, Pol Lin ; Liu, Chii Tung ; Wang, Jia Shung
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
1
fYear :
2000
fDate :
2000
Firstpage :
465
Abstract :
In wavelet-based video compression, some kernel functions such as block matching, discrete wavelet transform, are essential but with large complexity in computation. If we dissect two functions into the basic matrix-vector product forms, a unified design for them becomes feasible. In this paper, with carefully extraction the common computation component, a unified one-dimensional systolic array that can perform block matching and wavelet transform is presented. In this design, the input data is serial-in to save the amount of required pins, the data flow are carefully arranged to simplify the interconnection between computation components. Unlike the other full-search block matching hardware, it does not require either data broadcasting or the parallel adder. When executing a wavelet transform, the data flow is scheduled simply and effectively. It does not require any interconnecting network or off-chip memory to store intermediate results
Keywords :
data compression; discrete wavelet transforms; image matching; systolic arrays; video codecs; block matching; discrete wavelet transform; kernel functions; matrix-vector product forms; one-dimensional systolic array; unified systolic array design; video compression; wavelet-based video codec; Data flow computing; Data mining; Discrete wavelet transforms; Hardware; Kernel; Pins; Systolic arrays; Video codecs; Video compression; Wavelet transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
Type :
conf
DOI :
10.1109/ICECS.2000.911580
Filename :
911580
Link To Document :
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