CAD tools for synthesis

A few years ago, the electronic design process in the majority of ASIC and system design companies was based on a capture-and-simulate design methodology. The front-end tool used was the schematic editor which constituted the way to generate the major portion of the logic network. RT and logic synthesis represent the key design technology in top-down design methodologies. They have meant a revolutionary change of the capture-and-simulate methodology into a describe-simulate-and-synthesize methodology based on the use of hardware description languages (HDLs). This novel methodology makes use of a new generation of synthesis tools which play a key role in industrial digital design due to the increased productivity they provide. VHDL is the language most widely used for synthesis. Nevertheless, VHDL was developed as a language for modeling applications and, as a consequence, its use for synthesis applications is not straightforward. This contribution covers the main topics concerning the use of these new CAD tools for synthesis using VHDL