DocumentCode :
2969571
Title :
A novel high-performance fault-tolerant ICAP controller
Author :
Ebrahim, Ali ; Benkrid, Khaled ; Iturbe, Xabier ; Hong, Chuan
Author_Institution :
Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK
fYear :
2012
fDate :
25-28 June 2012
Firstpage :
259
Lastpage :
263
Abstract :
Dynamic Partial Reconfiguration is an important feature of modern FPGAs as it allows for better exploitation of FPGA resources over time and space. The Internal Configuration Access Port (ICAP) enables DPR from within an FPGA chip, leading to the possibility of fully autonomous FPGA-based systems. This paper presents a novel high performance and fault-tolerant ICAP controller which can operate at a high speed and recover from emerging faults. Test results showed that our ICAP controller is 25 times faster than the Xilinx´ XPS_HWICAP IP core. We demonstrate the use of Triple Modular Redundancy (TMR) in some of the ICAP controller components which have the ability to reconfigure the rest of the ICAP controller when faults are detected. This method is shown to have a 49% smaller area footprint compared to traditional full TMR.
Keywords :
fault tolerant computing; field programmable gate arrays; microcontrollers; FPGA chip; ICAP controller component; Xilinx´ XPS_HWICAP IP core; fault; fault-tolerant ICAP controller; high-performance fault-tolerant ICAP controller; internal configuration access port; triple modular redundancy; Circuit faults; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Process control; Tunneling magnetoresistance; Dynamic Partial Reconfiguration; FPGA; ICAP; TMR;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Adaptive Hardware and Systems (AHS), 2012 NASA/ESA Conference on
Conference_Location :
Erlangen
Print_ISBN :
978-1-4673-1915-7
Electronic_ISBN :
978-1-4673-1914-0
Type :
conf
DOI :
10.1109/AHS.2012.6268660
Filename :
6268660
Link To Document :
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