Digit recurrence divider: Optimization and verification

In this paper, we present the division computation by the SRT algorithm. This last is characterized by the linear convergence, i.e., at each iteration, one quotient digit is obtained as result. Thus, increasing a radix, the iterations number decreases, but the hardware complexity increases which involve the use of a multiplier to calculate the product of quotient digit by the divider. For this purpose and for an implementation on a Xilinx FPGA circuit, we propose for a radix-8 and a maximum redundancy factor, an approach to divert the multiplication. This approach consists of the decomposition of the quotient digits into two terms power of 2. In this way, the multiplication is carried out by shifts and one addition. The implementation results revealed an iteration time of 11,7 ns.