Incrementally recompiling Verilog

One of the frustrations frequently encountered by users of high level design languages is the large amount of time required to process small changes in the design. This frustration is particularly acute in the final stage of hardware design when using a hardware description language like Verilog or VHDL. Since hardware models tend to be quite large and changes made quite small, any non-incremental approach to design processing pays a high overhead in time required to evaluate a change. Obviously, hardware designers will benefit tremendously using the incremental recompilation capability in high level design language, if one exists. We present our experience in the design and implementation of incremental design recompilation in our Verilog Compiled Code Simulator, VCS