Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

This paper presents the work regimes of an atypical SOI device. The proposed device belongs to the Tunneling FET class, but the main body is a vacuum cavity. Each layer has a maximum of 10 nm. Firstly, the paper studies the static characteristics of the proposed device by simulations for different semiconductor materials: Si, SiC and Ge, with different doping concentrations, in different bias conditions. Secondly, some key parameters are defined in order to establish the boundary of the different work regimes. The normal work regime is conditioned by the useful tunneling occurrence, maximum transconductance, and current capability, far away from the insulator breakdown that means a non-useful back-gate leakage current. The simulations reveal optimum Semiconductor-Vacuum-Semiconductor structures On Insulator for heavy doped films, thin oxides, and larger band gap materials. An optimum balance is offered by the SiC device with 10 nm thickness on 10 nm insulator with a cavity width of 2 nm.