Hardware efficient architectures for coupled-form IIR filters

Second-order coupled-form IIR filters have the signals in their upper and lower feedback branches coupled and processed concurrently. By use of multirate signal processing techniques, we convert this concurrent signal processing to sequential processing. Thus we obtain an interpolated coupled-form IIR filter. The hardware implementation of interpolated coupled-form IIR filters is discussed and hardware efficient architectures are proposed. We estimate the hardware complexity for a typical case with CSD (canonic signed digit) multipliers having three canonic signed digits and an input signal having a wordlength of eight bits. Without losing throughput, up to a 22% hardware reduction can be obtained for the second-order coupled form IIR filter and about 48% for the fourth-order coupled-form IIR filter